The subject matter discussed in the background section should not be assumed to be prior art merely as a result of its mention in the background section. Similarly, a problem mentioned in the background section or associated with the subject matter of the background section should not be assumed to have been previously recognized in the prior art. The subject matter in the background section merely represents different approaches, which in and of themselves may also correspond to embodiments of the claimed subject matter.
Conventional hierarchical caching design requires that cache requests from a higher level cache first allocate a buffer and then issue a subsequent request to the higher level cache of the specific cache line that is required. Later, when the required cache line arrives, it is written into the buffer previously allocated. When the request from the higher level cache is completed and all necessary request attributes returned to the allocated buffer now having the cache line required, the buffer is made ready for a replace operation such that the required cache line now stored in the allocated buffer can be inserted or replaced into the lower level cache. At this stage, the required cache line is not in the lower level cache where it is required, but rather, it is buffered and is now ready to be placed into the lower level cache.
A scheduler will later pick the allocated buffer having the required cache line from among all existing buffers in a ready state, and then the required cache line will be moved from the buffer and into the lower level cache via either a replace (e.g., eviction of another cache line) or an insert. The allocated buffer is no longer required and thus, is de-allocated, and at this stage, the required cache line is available within the lower level cache to whatever entity, operation, or requestor requires the cache line.
Because the replace or insert operation of the required cache line into the lower level cache must utilize a free read and write port to perform its insertion, all other cache stores and cache load operations with the cache are stalled to free the necessary read and write port, thus permitting the insertion of the required cache line into the lower level cache to proceed.
The conventionally implemented protocol for retrieving a cache line from a higher level cache into a lower level cache where it is required therefore suffers from at least two major problems. First, low throughput for such requests is exhibited due to a long buffer lifetime. Secondly, brutal or forced read and write port takeovers degrade performance yet are required in every instance.
The present state of the art may therefore benefit from systems and methods for implementing efficient communication between caches in hierarchical caching design as described herein.